Grant’s 7-chip Z80 computer

Posted by musovern on May 10th, 2018 in Grant's 7 Chip Z80, Single Board Computers | 0 comments

This is my version of Grant Searle’s 7-chip Z80 computer that i made on veroboard a few years back a very simple Z80 design.

The purpose of this computer is to create the simplest possible machine with a high speed interface, good amount of RAM and also a good implementation of BASIC.
The design that Grant produced is shown here, and is probably the simplest Z80 circuit that can be done to fulfill what I needed.

 

 

 

 

 

 

 

 

 

Circuit description.

A Z80 memory read is determined whenever the /MREQ pin goes low when the /RD pin or /WR pin is also low. Two OR gates are used to combine the memory access (/MREQ) and the read/write signals (RD/WR) to produce “memory read” and “memory write” to simplify the interfacing to the ROM and RAM. These are then connected to the appropriate pins on the ROM and RAM devices. Address decoding using A13,A14 and A15 will identify the lower 8K (low when A13,A14 and A15 are all low).

This is connected to the active-low chip select of the ROM and also to the active-high chip select of the RAM. This way, either the ROM will be active (lower 8K) otherwise the RAM will be active (the remaining 56K). The entire 64K memory space is therefore used.

The serial interface is accessed using the Z80 I/O addressing mechanism. When accessing I/O devices, the /IORQ signal is taken low along with /RD or /WR. The 6850 does not follow this convention, however, as it is uses a single Enable (E) pin, along with a single R/W pin to identify whether a read or write is to be performed. The R/W pin is taken directly to the /WR pin of the Z80 and the Enable pin is taken to an inverted signal from the /IORQ.

 

A problem exists, however, as the /IORQ is also taken low during an interrupt acknowledge. If this was allowed, then the data/control values in the serial interface would be corrupted when the interrupt is acknowledged by the Z80. Interrupt acknowledge is identified by /IORQ and /M1 signals going low, so the 6850 is to be disabled if /M1 is low (the Z80 /M1 signal connected to the active-high CS0 of the 6850). This ensures that only real I/O triggers the serial interface. The /M1 signal is much wider than the /IORQ and totally masks the /IORQ signal. This ensures that there is no possibility of the ACK signal enabling a read or write. The remaining chip selects on the serial interface are connected to A7 and A6, so any I/O on address 10xxxxxx will select the serial chip. Finally, the register select on the serial interface is connected to A0, so the control register is addressed on port 80H and the data register is addressed on port 81H.

The remaining chip is a MAX232 (or MAX202) which is a level converter to convert the TTL signals to RS232 values.